The present invention relates to an improved parallel signal transmission system operating with reduced power consumption.
A signal transmission system, including a transmitter unit, a receiver unit and a plurality of signal lines interposed between these units, is well known in the art. The total number of signal lines is prescribed based on the maximum amount of information to be transmitted. The transmitter unit includes a plurality of drivers each connected to associated one of the signal lines. For example, each of these drivers includes: a PMOS transistor interposed between a power line (voltage VDD) and an associated signal line; and an NMOS transistor interposed between the associated signal line and a ground line (voltage VSS).
High-speed signal transmission among a plurality of semiconductor integrated circuit chips mounted on a single printed wiring board is now in high demand. For example, in processing an enormous amount of moving picture data, a parallel signal transmission technique is employed to transmit address signals, data signals and other control signals between a memory controller and a memory. The higher the speed of signal transmission of this type is, the more noticeably a signal waveform is affected by reflection resulting from the inductance of a signal line. Thus, each of the signal lines used for parallel signal transmission is connected to a terminal voltage line (voltage VTT) via a low-impedance terminal resistor. The terminal voltage VTT is set approximately at (VDD+VSS)/2, for example.
Assume each of the signal lines used for parallel signal transmission among semiconductor integrated circuit chips is connected to a terminal resistor. Then, if the output of a driver is logic "1" (i.e., if the PMOS transistor in the driver is ON), direct current flows from the power line (voltage VDD) through the PMOS transistor and the associated signal line and terminal resistor into the terminal voltage line (voltage VTT). Conversely, if the output of a driver is logic "0" (i.e., if the NMOS transistor in the driver is ON), then direct current flows from the terminal voltage line (voltage VTT) through the associated terminal resistor and signal line and the NMOS transistor into the ground line (voltage VSS). All of these drivers and terminal resistors always generate these direct currents. Accordingly, the power consumed due to the generation of direct current is non-negligibly high.
In performing parallel signal transmission among circuit blocks in a single semiconductor integrated circuit chip, a signal line is not connected to a terminal resistor unlike chip-to-chip parallel transmission. Instead, direct current resulting from charging/discharging of parasitic capacitance associated with each signal line is always generated in every driver. Accordingly, the power consumed due to the generation of direct current is also non-negligibly high.